1. Field of the Invention
This invention relates to MOS devices and in particular to a method for reducing the current gain of parasitic bipolar junction transistors within the MOS structure.
2. Description of Prior Art
FIG. 1 shows a typical low voltage N-well MOS transistor 5 which can be part of a CMOS structure. P substrate 10 has diffused into it N-well region 15 about 3-10 microns deep. P+ source region 20, P+ drain region 25, and N-well region contact 27, are then diffused into N-well region 15. Control gate 30 is formed over and insulated from channel region 35, channel region 35 being the region between source region 20 and drain region 25. Normal operating voltages and connections are as follows: P substrate 10 is grounded or at a negative voltage; N-well region 15 is at a positive voltage V.sub.ss with respect to P substrate 10 so as to reverse bias N-well region 15 and P substrate 10; P+ source 20 is shorted to N-well region 15; P+ drain 25 is connected to load 38; and, control gate 30 is connected to input voltage V.sub.in.
The structure of FIG. 1 is susceptible to over-current damage if the parasitic PNP transistor, formed by P+ drain 25, N-well 15, and P substrate 10, is biased into its active mode and conducts a high current between P+ drain 25 and P substrate 10. One way in which this parasitic PNP transistor may be turned on is that if load 38, connected to P+ drain 25, is inductive, a high voltage may result from the rapid di/dt turn-off of transistor 5. This high voltage generated by the load forward biases the P-N junction formed between P+ drain 25 and N-well 15. Since the junction between N-well 15 and P substrate 10 is reverse biased, the parasitic PNP transistor is biased into its active mode. Noise from the load into the drain can also cause parasitic transistor turn-on, even when the MOS transistor is on, if the noise voltage is greater than 0.7 v above the N-well voltage.
One way to reduce the current through a parasitic PNP or NPN transistor is to reduce its current gain by forming a highly doped buried region of the same conductivity type as the well region below and contiguous with the well region. This buried layer creates a built-in electric field which is in a direction that opposes the transit of minority carriers across the base, or well, and also widens the base region. This increased base width, along with an increased Gummel number (i.e., total charge in the base region), results in almost total recombination of the injected minority carriers within the base region.
In low voltage CMOS structures parasitic bipolar junction transistors are formed, as shown in FIG. 2, which can cause latch-up Latch-up occurs in a low voltage CMOS structure due to a four layer NPNP or PNPN path.
Turn-on of parasitic bipolar junction transistors in CMOS structures can be largely eliminated by forming a buried region below the well, thus forming a retrograde well, in order to reduce the loop current gain of the parasitic transistor pair to below unity. This buried region has been experimentally demonstrated and shown to reduce gain by as much as two orders of magnitude. This method to reduce parasitic transistor current gain in low voltage CMOS structures is discussed in the following references: "Latch-Up Control in CMOS Integrated Circuits", by A. Ochoa et al., IEEE Trans. Nucl. Sci., Vol. NS-26., No. 6, December 1979; "An Analysis of Latch-Up Prevention in CMOS ICs Using An Epitaxial Buried Layer Process", by D. Estreich et al., International Electron Device Meeting, Washington, D.C. 1978; and the book, "Latch-Up in CMOS Technology", by R. Troutman, Kluwer Academic Publishers, Boston, 1986. These three references are herein incorporated by reference.
A typical doping profile for an NMOS transistor with a retrograde P-well is shown in FIG. 3. In the references mentioned above, the same type implant (e.g., boron) was used to form the P+ buried region and P-well. As an example, Estreich et al. describe a method for forming a low voltage CMOS structure by, inter alia, implanting boron into an N substrate to form a P+ buried layer, forming an N- epitaxial layer over the buried layer, and then implanting boron into the epitaxial layer to form the P-well. The P+ buried layer and the P-well then diffuse together in what is called an up-down method to form the retrograde well.
In prior art high voltage MOS transistors, wells formed using the up-down method which incorporate a buried layer are not used due to the likelihood that the high concentration of impurities in the buried layer will diffuse into the well region and reduce the breakdown voltage of the device. Breakdown voltage would be reduced since the depletion region between a P+ drain and a highly doped N-well region spreads very little with an increase in reverse bias voltage, consequently, the electric field between the P+ drain and N-well increases, eventually causing breakdown. Deeper diffused N-wells (e.g., greater than 10 microns) are not practical due to the long drive-in times required. Prior art high voltage MOS transistors typically use more expensive deep "tubs", which are isolated portions of an epitaxial layer of a conductivity type opposite that of the substrate, in conjunction with a highly doped buried layer of the same conductivity type as the epitaxial layer, as shown in FIG. 4, to reduce the current gain of the parasitic bipolar transistor.
FIG. 4 shows a typical high voltage MOS transistor 40 with N+ buried layer 42 formed to reduce the current gain of the parasitic PNP transistor formed by P+ drain region 49, N- epitaxial layer 45, and P substrate 41. In FIG. 4, transistor 40 is formed starting with P substrate 41 and diffusing an N type dopant, such as arsenic, into substrate 41 to subsequently form N+ buried layer 42. A P type dopant, such as boron, is then implanted to subsequently form isolation region 44. N- epitaxial layer 45 is then grown on P substrate 41 and dopants used to form buried layer 42 and isolation region 44 diffuse up into epitaxial layer 45. P type dopants are then introduced from above to form isolation region 46 which merges with isolation region 44 to isolate transistor 40 from other devices within epitaxial layer 45. P type dopants are then introduced to form P+ source region 48, P+ drain region 49, and P- drift region 50 contiguous with drain region 49. N type dopants are introduced to form N+ contact region 51. The P+ isolation regions in FIG. 4 are formed in a lengthy process using an up-down method, where diffusion from below and above an epitaxial layer merge together to form one continuous diffusion region.
What is needed in the art is a method to form a deep well and buried layer in an epitaxial layer and semiconductor substrate which would have a high breakdown voltage and reduce parasitic transistor current gain. This well would obviate the need to form isolation regions of a conductivity type opposite that of the epitaxial layer to isolate the MOS transistor from other devices and would save processing time.